"Progressively" scanned television receivers have been proposed wherein the horizontal scan rate is multiplied, i.e., doubled, and each line of video is displayed twice thereby providing a displayed image having reduced visibility of line structure and subjectively improved vertical resolution. In a typical progressively scanned receiver, each line of video is stored in one of two memories. As a first of the memories is being written with the incoming video signal at a standard line rate, the second of the memories is read two times at twice the standard line rate thereby providing two lines of "speed-up" (time-compressed) video within one standard line interval. The second memory output is applied to a display having a doubled horizontal sweep rate synchronized with read-out of the memory thereby doubling the number of displayed lines of video signal. An example of such a progressively scanned receiver, wherein the added lines of video signal are replicas of the original scan lines, is described in U.S. Pat. No. 4,415,931 entitled TELEVISION DISPLAY WITH DOUBLED HORIZONTAL LINES which issued Nov. 15, 1983 to R. A. Dischert.
It has been recognized that a desirable reduction of certain artifacts (e.g., inter-line flicker, line break-up with motion, etc.) may be obtained in a progressively scanned receiver by interpolating the added lines of the video signal from the original signal. This may be done either before or after "speed-up" (i.e, time compressing) of the video signal in the memory. An example of a progressively scanned display system in which the additional scan lines are obtained by interpolation from the original scan lines prior to time compression or video "speed-up" is described by K. H. Powers in U.S. Pat. No. 4,400,719 entitled TELEVISION DISPLAY SYSTEM WITH REDUCED LINE SCAN ARTIFACTS which issued Aug. 23, 1983. An alternative of providing interpolation subsequent to speed-up of the video signal is described by Yasushi Fujimura et al. in UK Patent Application No. 2,111,343A published June 29, 1983. In these interpolating progressive scan receivers separate clocked memories (e.g., CCD or a RAM) are connnected in cascade for providing the interpolation and speed-up functions.
The use of separate clocked memories in cascade for providing the functions of interpolation and time compression can result in a requirement for meeting very critical clock timing requirements. This problem arises because where memories are cascaded, the first memory in the cascade connection must "settle" before the information recovered from it can be written into the second memory and the settling time may comprise a significant portion of a clock cycle. The read clock in an NTSC processor, for example, typically operates at a frequency of about 28 MHz (i.e., eight times the color subcarrier frequency, 8 f.sub.sc) and thus has a period of only about 35 nano-seconds. To meet this timing requirement, and to allow a reasonable margin for manufacturing tolerances, it may be necessary to resort to the use of multiphase clocks or to use special clock delay lines to properly time the operation of separate interpolator and time compressor memories.